Trust before autonomy
IP isolation, grounding, audit, human-in-the-loop and graduated control. The level is a dial the fab turns.
About
The fab has the sensors, the metrology and the traceability. What it lacks is autonomy.
Waferira exists to give every semiconductor front-end fab a system that turns the data it already collects into action on the next wafer: hitting yield, uniformity and cycle time on every lot and turning reactive, engineer-bound process control into a closed perceive, decide, act loop. The vision is to become the autonomous operations layer for the world's semiconductor front-end manufacturing.
Mission
Give every fab the autonomy to hit yield, uniformity and cycle time on every lot
Turning reactive, engineer-bound process control into a closed perceive, decide, act loop, with the fab's IP never leaving its walls.
VisionBecome the autonomous operations layer for the world's semiconductor front-end manufacturing.
Why
Why we are building this
The fact on the fab floor that started it.
A front-end fab is the most capital-intensive, precise and complex factory humanity has built. A wafer passes 700 to 1,500 steps over months, every layer has to hit nanometer overlay, CD, film thickness and uniformity across thousands of tools, and a few stray nanometer-scale defects can destroy a lot worth hundreds of thousands to millions of dollars.
Yet most fabs still run largely reactive process control, manual defect review and rule-based dispatch, paced by a scarce and shrinking process and yield engineering workforce drowning in metrology, inline-defect, tool-sensor and FDC data. The data is all there. The loop between seeing a problem and acting on it is still mostly human.
Why now
- The AI-accelerator and compute boom, HBM and memory and advanced-logic ramps
- Fab build-out and reshoring under the CHIPS Act and its equivalents
- Advanced-node and 3D complexity, cost-per-wafer pressure and multi-million-dollar lot scrap
- A severe, scarce process and yield engineering workforce
- AI defect classification, virtual metrology, run-to-run APC, edge AI, AMHS robotics and fab twins have matured for production fabs
Principles
How we build
The guiding principles from our own roadmap.
Compounding data
Every supervised correction trains the system. The closed-loop control corpus, per tenant, is the asset.
Land narrow, expand
One module, one metric, one baseline agreed in writing. Then the fab. Then the group.
Cite everything
Every answer from the reasoning layer carries its source. Every action carries its evidence.
Isolate tenants
Recipes, device designs, models and memory never cross a customer boundary. On-prem for those who need it.
Say what is planned
Figures are design targets until they are measured. Scenarios are labelled scenarios.
Focus
What kind of company this is
For anyone checking eligibility or category.
- An independent startup building original Physical AI software for semiconductor front-end wafer fabrication
- A product company, not a consultancy, systems integrator, reseller or outsourced development shop
- Not a cloud provider and not associated with cryptocurrency
- Pre-launch and pre-revenue. Incorporation, headquarters, founders and headcount are not published yet and nothing on this site should be read as claiming them
Run timeline · scenario
What we are actually building
Every Waferira run is an ordered, inspectable sequence. This is run_7b2e9c on Module M2 · 300 mm · metal-1 · lot L-48213. Scenario completes in 10 steps with one approval gate. Overlay and CD predicted inside spec, one reticle-repeater signature caught and held for review, dispatch re-optimised, lot released with full genealogy.
run_7b2e9c
Module M2 · 300 mm · metal-1 · lot L-48213
illustrative scenario
SUCCEEDED
-
01
ingest.lot
SUCCEEDED
0.7 s
Fab Orchestrator · Pulled lot L-48213 from fab MES: 25 wafers, 300 mm, metal-1 layer, route, reticle, overlay and CD spec and the standing cycle-time target. Locked the target envelope for the run.
-
02
twin.simulate
SUCCEEDED
38 s
Fab Twin · Simulated 64 candidate correctable, recipe and dispatch sets on the as-run fab twin and ranked them on predicted overlay residual, CD uniformity, excursion risk and cycle time.
-
03
litho.correctables
SUCCEEDED
1 m 20 s
Litho-and-Overlay · Per-field overlay correctables and a focus-dose trim written to scanner SCN-07 over SECS/GEM after the previous lot's residual trended toward the control limit. Predicted overlay residual back inside spec.
-
04
etch.uniformity
SUCCEEDED
58 s
Etch-and-Depo · Chamber B on etcher ETCH-12 showed an edge-fast uniformity drift in FDC. Pressure and RF trims written within the qualified recipe window; predicted CD uniformity recovered.
-
05
cmp.removal
SUCCEEDED
46 s
CMP-and-Implant · Downforce and platen-speed trim on CMP-03 against the virtual removal-rate estimate to hold post-CMP thickness and dishing inside the window.
-
06
inspect.classify
SUCCEEDED
continuous
Defect-and-Inspect · Inline optical, e-beam review and SEM imagery fused at the tool edge. 1,412 events classified, most dispositioned nuisance; one reticle-repeater signature on three dies flagged for review.
-
07
vm.score
SUCCEEDED
2.1 s
Metrology-and-Virtual · Virtual metrology scored every wafer at post-etch and post-CMP from tool-sensor and FDC signatures. Two wafers routed to physical metrology on predicted variance; the rest sampled at plan.
-
08
approve.human
APPROVAL
1 m 04 s
Fab Orchestrator · The reticle-repeater signature called for a reticle inspection hold and a recipe move outside the qualified window. Held for the module process engineer and approved at 03:14:27.
-
09
dispatch.route
SUCCEEDED
4.3 s
Yield-and-Dispatch · Dispatch re-optimised across 1,840 lots in WIP under reticle, chamber and qualification constraints. The lot routed to the qualified chamber with the shortest predicted queue; AMHS move issued to the stocker.
-
10
lot.release
SUCCEEDED
1 m 05 s
Quality-and-Conformance · Lot L-48213 moved on: genealogy written (recipe moves, correctables, FDC signatures, VM scores, defect map, approvals) and checked against the layer spec.
Market
The market
Figures are the company's own estimates.
$28BTotal addressable spend: fab automation, APC, inspection, metrology, yield management, MES and fab software
$7BServiceable with Waferira's product and go-to-market
$360MRealistically obtainable within three years, an estimate
~14%Estimated annual growth of the addressable spend
Team
Who is building it
Waferira is led by its co-founders, Sebastian Ward (CEO) and Adrian Phillips (CTO). Backgrounds are published here once they can be checked.
Co-Founder & CEO
Sebastian Ward
Sebastian owns the design-partner relationships, the pilot structure and the commercial model, starting with the fab modules where yield excursions and rework cost the most.
Co-Founder & CTO
Adrian Phillips
Adrian owns the fab-edge runtime, the perception and process-control models, the wafer-and-tool digital twin and the audit architecture behind every Waferira agent.
Hiring
The founding roles we expect to open are on the careers page: fab-edge perception, APC and tool integration, simulation and twin, and a process integration engineer who has owned a module in production.
Writing
Recent from the blog
Rich data, reactive control
Fabs collect more data per wafer than any factory on earth, and still find excursions after the lots that ran through them are gone.
Autonomy is graduated, not switched on
No fab goes from manual APC to unattended control in one step. The level has to be explicit, auditable and reversible.
Hit yield before the lot runs
Fabs commit lots and node ramps blind. The twin changes the order of operations.
Accelerated computing
Physical AI, at the tool
Computational lithography, defect classification on e-beam and SEM imagery, per-wafer virtual metrology and a full-fab twin are among the most compute-intensive workloads in manufacturing. Waferira keeps IP-sensitive inference and feature storage at the fab edge and runs training, simulation and optimisation on GPUs the fab controls.
Inspection vision
Inline optical, e-beam and SEM imagery and sensor fusion on fab-edge GPUs. 10 to 50 inspection streams per pilot module and sub-200 ms priority defect triage are the design targets.
Virtual metrology and FDC
High-volume multivariate tool-sensor and FDC time-series scoring on every wafer, 1 to 5 seconds per lot-step in the design, with nightly retraining as recipes and chambers drift.
Training
Defect, virtual-metrology and process-response models retrained per process family; 500 to 2,000 GPU-hours per family per quarter is the design target. Dedicated capacity is planned.
Fab twin
As-run process and flow simulation, 1,000 to 10,000 candidate recipe, metrology and dispatch scenarios per fab per day in the design. OVX access is planned.
Synthetic rare events
Rare defect, particle, overlay-drift, CMP-dishing and film-uniformity variants generated and validated against real distributions before promotion. Planned.
Dispatch optimisation
Constrained WIP dispatch re-optimised every 1 to 5 minutes across reticle, chamber, route, tool-state and cycle-time constraints.
AMHS and handling
Local FOUP and robot perception and exception detection at the fab edge. Jetson Thor is planned for higher sensor density.
Process reasoning
Tenant-isolated process Q&A and OCAP reasoning over recipes, SEMI procedures and audit logs, with citations enforced on every answer.
Guardrails
An agent that can move a recipe needs a leash
Waferira writes to production tools over SECS/GEM. Every capability is scoped to a qualified recipe window, every write is policy-checked against tool state, and every action is written to an append-only, IP-isolated audit log the fab owns.
- Recipe bounds. Each agent writes only inside the qualified recipe window for that tool, with explicit per-parameter limits.
- Policy and tool-state checks before every write. Autonomy level, tool state, qualification, interlocks and shift are evaluated before a recipe moves.
- Human-in-the-loop gates. Holds, out-of-window moves and lot release wait for a named approver, with OCAP linkage on every excursion.
- Immutable, IP-isolated audit log. Append-only and exportable. Every action records source signals, retrieved procedures with citations, predicted impact, allowed range, rollback condition, approver and lot scope.
- Rollback. Declared rollback conditions return a recipe to its previous qualified version; loss of the edge node leaves the tool on its own controller and recipe.
- Tenant and IP isolation. Recipes, device designs, defect libraries and process memory never cross a customer boundary. Inference and feature storage stay at the fab edge; an on-prem control plane is available for IP-sensitive fabs.
Compliance posture
| Item | Scope | Status |
|---|---|---|
| SOC 2 Type I and fab-security review | Control plane | QUEUED Planned, first 6 months |
| SOC 2 Type II | Control plane | QUEUED Planned, 6 to 12 months |
| SSO and RBAC | Console and approvals | QUEUED Planned, 6 to 12 months |
| IP-isolation and security assurance package | Fab security and IT and OT review | QUEUED Planned, 6 to 12 months |
| SEMI-standards-cited reasoning | Recipes, integration specs, OCAPs | RUNNING In the design, every answer cites its source |
| Per-tenant IP isolation | Data, models, memory | RUNNING In the design from day one |
| On-prem and fab-edge deployment | IP-sensitive fabs | RUNNING Design option |
FAQ
Straight answers
The questions fab directors and process engineers ask in the first meeting.
Yes, over SECS/GEM, but only inside the qualified recipe window for that tool, with per-parameter limits and tool-state checks, and only at the autonomy level your fab has set. Level 1 is advisory: Waferira recommends and an engineer enters everything. Design partners start there, in shadow mode.
The tool stays on its own controller and its last qualified recipe. Waferira is a supervisory layer on top of the APC, inspection, metrology and MES systems you already run, never a replacement for them, so an outage leaves the module running the way it runs today.
No. Inference and feature storage stay at the fab edge, recipes, device designs, defect libraries and process memory are isolated per tenant, and an on-prem control plane is available for IP-sensitive fabs. Any cross-fab learning is planned, contract-gated and privacy-preserving, and none of it moves recipes or designs.
Advisory recommendations start from the existing APC, metrology and ADC data on the wedge module. Defect classification, virtual metrology and excursion prediction improve as labelled events and lot outcomes accumulate per process family. Rare excursions are augmented synthetically only after validation against real distributions.
You are, the same as with any APC strategy, which is why every write is policy-checked, bounded to the qualified window, logged and reversible, and why holds, out-of-window moves and lot release wait for a named approver with the OCAP linked.
A paid pilot on one process module or tool fleet, scoped to one wedge workflow with a baseline agreed in writing. Shadow mode first, observing and measuring the baseline. Then assist mode, where the agent recommends and your engineer approves and accuracy and ROI are measured. Then bounded autonomy for low-risk APC, defect or metrology loops if the fab is satisfied.