SECS/GEM on scanners, etchers, deposition, CMP, implanters, furnaces and wet benches
Recipe reads and bounded recipe writes
Waferira connects to the SECS/GEM tool integration, APC, inspection, metrology, FDC, yield-management, MES and AMHS systems already in a front-end fab and normalises their signals into one time-aligned wafer and lot record. Recipe writes go back through SECS/GEM, bounded to the qualified window.
Illustrative scenario: Module M2 · 300 mm · metal-1 · lot L-48213, one lot through metal-1, one approval gate
Waferira reads and writes through the systems already in the fab. No rip and replace, no parallel historian, no new HMI to learn. Vendor names are examples of systems found in front-end fabs; connector availability is confirmed per site.
SECS/GEM on scanners, etchers, deposition, CMP, implanters, furnaces and wet benches
Recipe reads and bounded recipe writes
Advanced and run-to-run process control systems (Applied Materials APF and APC, PDF Solutions, in-house IDM APC)
Model state, correctables, control limits
Inline optical, e-beam and SEM inspection and review tools (KLA, Applied Materials, Hitachi High-Tech, Onto Innovation class systems)
Images, defect maps, ADC classes
Overlay, CD, film and OCD metrology (KLA, Onto Innovation, Nova class systems)
Sampled measurements that ground virtual metrology
Fault-detection and tool-sensor streams per chamber
Per-wafer signatures for virtual metrology and prognostics
Yield and defect analytics (PDF Solutions Exensio, Synopsys, Siemens Camline, INFICON class systems)
Yield, bin and genealogy context
Fab MES and schedulers (Applied SmartFactory, Siemens Camstar, Critical Manufacturing, INFICON FPS class systems)
Lots, routes, WIP, dispatch lists
Stockers, vehicles and FOUP handling (Daifuku class AMHS)
Carrier moves and handling exceptions
Tenant-isolated time-series store for tool, metrology and yield telemetry; pgvector for defect images and recipe retrieval
Backfill, replay, retrieval
GPU inference nodes and Jetson at the tool, on-prem control plane option
Inference where the IP lives
Vendor names are examples of the systems found in front-end fabs, not certified integrations. Connector availability is confirmed during the shadow-mode phase of a pilot.
| Category | Examples in the fab | What Waferira does |
|---|---|---|
| Tool integration | SECS/GEM on scanners, etchers, deposition, CMP, implanters, furnaces and wet benches | Recipe reads and bounded recipe writes |
| APC and run-to-run | Advanced and run-to-run process control systems (Applied Materials APF and APC, PDF Solutions, in-house IDM APC) | Model state, correctables, control limits |
| Defect inspection | Inline optical, e-beam and SEM inspection and review tools (KLA, Applied Materials, Hitachi High-Tech, Onto Innovation class systems) | Images, defect maps, ADC classes |
| Metrology | Overlay, CD, film and OCD metrology (KLA, Onto Innovation, Nova class systems) | Sampled measurements that ground virtual metrology |
| FDC and tool sensors | Fault-detection and tool-sensor streams per chamber | Per-wafer signatures for virtual metrology and prognostics |
| Yield management | Yield and defect analytics (PDF Solutions Exensio, Synopsys, Siemens Camline, INFICON class systems) | Yield, bin and genealogy context |
| MES and scheduling | Fab MES and schedulers (Applied SmartFactory, Siemens Camstar, Critical Manufacturing, INFICON FPS class systems) | Lots, routes, WIP, dispatch lists |
| AMHS | Stockers, vehicles and FOUP handling (Daifuku class AMHS) | Carrier moves and handling exceptions |
| Stores | Tenant-isolated time-series store for tool, metrology and yield telemetry; pgvector for defect images and recipe retrieval | Backfill, replay, retrieval |
| Fab edge | GPU inference nodes and Jetson at the tool, on-prem control plane option | Inference where the IP lives |
The shadow-mode phase of a pilot.
Scope limits in version one.
Every Waferira run is an ordered, inspectable sequence. This is run_7b2e9c on Module M2 · 300 mm · metal-1 · lot L-48213. Scenario completes in 10 steps with one approval gate. Overlay and CD predicted inside spec, one reticle-repeater signature caught and held for review, dispatch re-optimised, lot released with full genealogy.
Fab Orchestrator · Pulled lot L-48213 from fab MES: 25 wafers, 300 mm, metal-1 layer, route, reticle, overlay and CD spec and the standing cycle-time target. Locked the target envelope for the run.
Fab Twin · Simulated 64 candidate correctable, recipe and dispatch sets on the as-run fab twin and ranked them on predicted overlay residual, CD uniformity, excursion risk and cycle time.
Litho-and-Overlay · Per-field overlay correctables and a focus-dose trim written to scanner SCN-07 over SECS/GEM after the previous lot's residual trended toward the control limit. Predicted overlay residual back inside spec.
Etch-and-Depo · Chamber B on etcher ETCH-12 showed an edge-fast uniformity drift in FDC. Pressure and RF trims written within the qualified recipe window; predicted CD uniformity recovered.
CMP-and-Implant · Downforce and platen-speed trim on CMP-03 against the virtual removal-rate estimate to hold post-CMP thickness and dishing inside the window.
Defect-and-Inspect · Inline optical, e-beam review and SEM imagery fused at the tool edge. 1,412 events classified, most dispositioned nuisance; one reticle-repeater signature on three dies flagged for review.
Metrology-and-Virtual · Virtual metrology scored every wafer at post-etch and post-CMP from tool-sensor and FDC signatures. Two wafers routed to physical metrology on predicted variance; the rest sampled at plan.
Fab Orchestrator · The reticle-repeater signature called for a reticle inspection hold and a recipe move outside the qualified window. Held for the module process engineer and approved at 03:14:27.
Yield-and-Dispatch · Dispatch re-optimised across 1,840 lots in WIP under reticle, chamber and qualification constraints. The lot routed to the qualified chamber with the shortest predicted queue; AMHS move issued to the stocker.
Quality-and-Conformance · Lot L-48213 moved on: genealogy written (recipe moves, correctables, FDC signatures, VM scores, defect map, approvals) and checked against the layer spec.
Every tool invocation, argument and result is written to an append-only, IP-isolated, human-readable log, and every reasoning step is expandable. Nothing about a run is hidden from the fab.
Plan, thought, action, observation, exactly as the orchestrator would record it.
Run lot L-48213 through metal-1 on module M2, hold overlay and CD inside the layer spec, catch any excursion before physical metrology, and dispatch on cycle-time target.
Simulate the lot on the twin first. Lead with litho so the correctables are right before etch, then trim etch and CMP against virtual metrology, keep inspection continuous, and hold anything outside the qualified window for a human.
The previous lot's overlay residual on SCN-07 trended toward the control limit. On the twin, a per-field correctable update with a small dose trim brings the predicted residual back to 2.6 nm without touching focus.
twin.simulate(candidates=64) returns set #41: per-field correctables and dose minus 0.3% on SCN-07, chamber B pressure and RF trims on ETCH-12, downforce minus 2% on CMP-03.
Set #41 predicts overlay residual 2.6 nm, CD uniformity inside window and excursion risk 0.05. Nine candidates cut cycle time further but routed the lot to an unqualified chamber and were discarded.
Execute set #41 under autonomy level L3: seven recipe writes inside the qualified window, the reticle hold and the out-of-window move routed to the module process engineer.
Reticle-repeater signature on three dies at 03:09:40 from the fused inspection stream. Virtual metrology routed two wafers to physical measurement on predicted variance.
Scenario complete. Overlay and CD predicted inside spec, the repeater held and reviewed with the OCAP linked, the lot dispatched to a qualified chamber and released with full genealogy.
Computational lithography, defect classification on e-beam and SEM imagery, per-wafer virtual metrology and a full-fab twin are among the most compute-intensive workloads in manufacturing. Waferira keeps IP-sensitive inference and feature storage at the fab edge and runs training, simulation and optimisation on GPUs the fab controls.
Inline optical, e-beam and SEM imagery and sensor fusion on fab-edge GPUs. 10 to 50 inspection streams per pilot module and sub-200 ms priority defect triage are the design targets.
High-volume multivariate tool-sensor and FDC time-series scoring on every wafer, 1 to 5 seconds per lot-step in the design, with nightly retraining as recipes and chambers drift.
Defect, virtual-metrology and process-response models retrained per process family; 500 to 2,000 GPU-hours per family per quarter is the design target. Dedicated capacity is planned.
As-run process and flow simulation, 1,000 to 10,000 candidate recipe, metrology and dispatch scenarios per fab per day in the design. OVX access is planned.
Rare defect, particle, overlay-drift, CMP-dishing and film-uniformity variants generated and validated against real distributions before promotion. Planned.
Constrained WIP dispatch re-optimised every 1 to 5 minutes across reticle, chamber, route, tool-state and cycle-time constraints.
Local FOUP and robot perception and exception detection at the fab edge. Jetson Thor is planned for higher sensor density.
Tenant-isolated process Q&A and OCAP reasoning over recipes, SEMI procedures and audit logs, with citations enforced on every answer.
Waferira writes to production tools over SECS/GEM. Every capability is scoped to a qualified recipe window, every write is policy-checked against tool state, and every action is written to an append-only, IP-isolated audit log the fab owns.
| Item | Scope | Status |
|---|---|---|
| SOC 2 Type I and fab-security review | Control plane | QUEUED Planned, first 6 months |
| SOC 2 Type II | Control plane | QUEUED Planned, 6 to 12 months |
| SSO and RBAC | Console and approvals | QUEUED Planned, 6 to 12 months |
| IP-isolation and security assurance package | Fab security and IT and OT review | QUEUED Planned, 6 to 12 months |
| SEMI-standards-cited reasoning | Recipes, integration specs, OCAPs | RUNNING In the design, every answer cites its source |
| Per-tenant IP isolation | Data, models, memory | RUNNING In the design from day one |
| On-prem and fab-edge deployment | IP-sensitive fabs | RUNNING Design option |
The questions fab directors and process engineers ask in the first meeting.
Yes, over SECS/GEM, but only inside the qualified recipe window for that tool, with per-parameter limits and tool-state checks, and only at the autonomy level your fab has set. Level 1 is advisory: Waferira recommends and an engineer enters everything. Design partners start there, in shadow mode.
The tool stays on its own controller and its last qualified recipe. Waferira is a supervisory layer on top of the APC, inspection, metrology and MES systems you already run, never a replacement for them, so an outage leaves the module running the way it runs today.
No. Inference and feature storage stay at the fab edge, recipes, device designs, defect libraries and process memory are isolated per tenant, and an on-prem control plane is available for IP-sensitive fabs. Any cross-fab learning is planned, contract-gated and privacy-preserving, and none of it moves recipes or designs.
Advisory recommendations start from the existing APC, metrology and ADC data on the wedge module. Defect classification, virtual metrology and excursion prediction improve as labelled events and lot outcomes accumulate per process family. Rare excursions are augmented synthetically only after validation against real distributions.
You are, the same as with any APC strategy, which is why every write is policy-checked, bounded to the qualified window, logged and reversible, and why holds, out-of-window moves and lot release wait for a named approver with the OCAP linked.
A paid pilot on one process module or tool fleet, scoped to one wedge workflow with a baseline agreed in writing. Shadow mode first, observing and measuring the baseline. Then assist mode, where the agent recommends and your engineer approves and accuracy and ROI are measured. Then bounded autonomy for low-risk APC, defect or metrology loops if the fab is satisfied.
Start with one process module or tool fleet and one measurable baseline. A paid, IP-isolated pilot on defect classification, virtual-metrology-driven overlay and CD control or uniformity APC shows the number before you commit further.
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