Careers

Work on software that writes a recipe to a scanner.

Waferira is pre-launch and building its founding team. The four roles below are the ones we expect to open first, written as honestly as we can about the stage: there is no office to show, no customer list, and the first job is a paid, IP-isolated pilot on one module.

4 founding rolesPre-launchEdge, APC, simulation, process

run_7b2e9c · agent graph · module M2 · scenario 10 nodes · 1 approval gate
01 · orchestrator ingest.lot ✓ SUCCEEDED 02 · fabtwin twin.simulate ✓ SUCCEEDED 03 · litho_overlay litho.correctables ✓ SUCCEEDED 04 · etch_depo etch.uniformity ✓ SUCCEEDED 05 · cmp_implant cmp.removal ✓ SUCCEEDED 06 · defect_inspect inspect.classify ✓ SUCCEEDED 07 · metrology_vm vm.score ✓ SUCCEEDED 08 · orchestrator approve.human ◆ APPROVAL 09 · yield_dispatch dispatch.route ✓ SUCCEEDED 10 · quality_conf lot.release ✓ SUCCEEDED

Illustrative scenario: Module M2 · 300 mm · metal-1 · lot L-48213, one lot through metal-1, one approval gate

Founding roles

Where we need people

Role descriptions, not an openings count. Each is a founding role.

Founding role · 01

Founding fab-edge perception engineer

Metropolis, DeepStream, Holoscan, TensorRT on fab-edge GPUs and Jetson. Fuse optical, e-beam and SEM inspection streams into one defect classifier at tool cadence.

Founding role · 02

Founding APC and tool-integration engineer

SECS/GEM, APC and FDC connectors on litho, etch, deposition and CMP tools. Bounded recipe writes, tool-state checks, rollback and the IP-isolated audit log.

Founding role · 03

Founding simulation and twin engineer

Omniverse fab twin, physics-ML process surrogates, discrete-event flow simulation, cuOpt dispatch. Hit yield, uniformity and cycle time before the lot runs.

Founding role · 04

Founding process integration engineer

Someone who has owned a litho, etch or CMP module in a production fab. Translate process and yield craft into process windows, metrics and acceptance tests for design partners.

How we work

Six things about working here

01

The fab is the customer

We measure ourselves on yield points, excursions, scrapped lots, review hours and cycle time, the fab's own numbers.

02

Nothing unlabelled

A design target is called a design target. A scenario is called a scenario. We do not round up.

03

IP isolation is a feature

Per-tenant isolation, the policy engine, approvals and the audit log are the product, not overhead.

04

Simulate first

A recipe move is rehearsed on the twin before it is written. So are our own changes.

05

Write it down

Every decision, every run, every correction goes into a record someone else can read.

06

Go to the fab

The craft we are encoding lives on the floor and in the review room. We go there, under the fab's rules.

Run timeline · scenario

What you would be building

Every Waferira run is an ordered, inspectable sequence. This is run_7b2e9c on Module M2 · 300 mm · metal-1 · lot L-48213. Scenario completes in 10 steps with one approval gate. Overlay and CD predicted inside spec, one reticle-repeater signature caught and held for review, dispatch re-optimised, lot released with full genealogy.

run_7b2e9c Module M2 · 300 mm · metal-1 · lot L-48213 illustrative scenario SUCCEEDED
  1. 01 ingest.lot SUCCEEDED 0.7 s

    Fab Orchestrator · Pulled lot L-48213 from fab MES: 25 wafers, 300 mm, metal-1 layer, route, reticle, overlay and CD spec and the standing cycle-time target. Locked the target envelope for the run.

  2. 02 twin.simulate SUCCEEDED 38 s

    Fab Twin · Simulated 64 candidate correctable, recipe and dispatch sets on the as-run fab twin and ranked them on predicted overlay residual, CD uniformity, excursion risk and cycle time.

  3. 03 litho.correctables SUCCEEDED 1 m 20 s

    Litho-and-Overlay · Per-field overlay correctables and a focus-dose trim written to scanner SCN-07 over SECS/GEM after the previous lot's residual trended toward the control limit. Predicted overlay residual back inside spec.

  4. 04 etch.uniformity SUCCEEDED 58 s

    Etch-and-Depo · Chamber B on etcher ETCH-12 showed an edge-fast uniformity drift in FDC. Pressure and RF trims written within the qualified recipe window; predicted CD uniformity recovered.

  5. 05 cmp.removal SUCCEEDED 46 s

    CMP-and-Implant · Downforce and platen-speed trim on CMP-03 against the virtual removal-rate estimate to hold post-CMP thickness and dishing inside the window.

  6. 06 inspect.classify SUCCEEDED continuous

    Defect-and-Inspect · Inline optical, e-beam review and SEM imagery fused at the tool edge. 1,412 events classified, most dispositioned nuisance; one reticle-repeater signature on three dies flagged for review.

  7. 07 vm.score SUCCEEDED 2.1 s

    Metrology-and-Virtual · Virtual metrology scored every wafer at post-etch and post-CMP from tool-sensor and FDC signatures. Two wafers routed to physical metrology on predicted variance; the rest sampled at plan.

  8. 08 approve.human APPROVAL 1 m 04 s

    Fab Orchestrator · The reticle-repeater signature called for a reticle inspection hold and a recipe move outside the qualified window. Held for the module process engineer and approved at 03:14:27.

  9. 09 dispatch.route SUCCEEDED 4.3 s

    Yield-and-Dispatch · Dispatch re-optimised across 1,840 lots in WIP under reticle, chamber and qualification constraints. The lot routed to the qualified chamber with the shortest predicted queue; AMHS move issued to the stocker.

  10. 10 lot.release SUCCEEDED 1 m 05 s

    Quality-and-Conformance · Lot L-48213 moved on: genealogy written (recipe moves, correctables, FDC signatures, VM scores, defect map, approvals) and checked against the layer spec.

Process

How hiring runs

  1. Write to us. What you would own, what you have built or run, and why the fab.
  2. A conversation. An hour on the problem, not a quiz.
  3. A working session. A real design question from the backlog, worked together.
  4. References and an offer. Founding terms, discussed openly.
Accelerated computing

Physical AI, at the tool

Computational lithography, defect classification on e-beam and SEM imagery, per-wafer virtual metrology and a full-fab twin are among the most compute-intensive workloads in manufacturing. Waferira keeps IP-sensitive inference and feature storage at the fab edge and runs training, simulation and optimisation on GPUs the fab controls.

Metropolis · DeepStream · Holoscan · TensorRT

Inspection vision

Inline optical, e-beam and SEM imagery and sensor fusion on fab-edge GPUs. 10 to 50 inspection streams per pilot module and sub-200 ms priority defect triage are the design targets.

CUDA · RAPIDS · Triton

Virtual metrology and FDC

High-volume multivariate tool-sensor and FDC time-series scoring on every wafer, 1 to 5 seconds per lot-step in the design, with nightly retraining as recipes and chambers drift.

DGX or HGX · CUDA · cuDNN

Training

Defect, virtual-metrology and process-response models retrained per process family; 500 to 2,000 GPU-hours per family per quarter is the design target. Dedicated capacity is planned.

Omniverse · OVX

Fab twin

As-run process and flow simulation, 1,000 to 10,000 candidate recipe, metrology and dispatch scenarios per fab per day in the design. OVX access is planned.

Cosmos · Omniverse Replicator

Synthetic rare events

Rare defect, particle, overlay-drift, CMP-dishing and film-uniformity variants generated and validated against real distributions before promotion. Planned.

cuOpt · RAPIDS

Dispatch optimisation

Constrained WIP dispatch re-optimised every 1 to 5 minutes across reticle, chamber, route, tool-state and cycle-time constraints.

Jetson Orin · Isaac · TensorRT

AMHS and handling

Local FOUP and robot perception and exception detection at the fab edge. Jetson Thor is planned for higher sensor density.

NIM · NeMo · Retriever · Guardrails · AI Enterprise

Process reasoning

Tenant-isolated process Q&A and OCAP reasoning over recipes, SEMI procedures and audit logs, with citations enforced on every answer.

Autonomy

Four levels, set per agent and per tool

A fab does not go from manual APC to unattended control in one step. Waferira makes the level explicit, auditable and reversible at any time. The first release runs shadow mode, then assist mode, then graduated autonomy for low-risk APC, defect and metrology loops.

Autonomy levels and the human role at each
LevelWhat the agent doesWhat the human doesWhere it sits in a pilot
L1 · AdvisoryRecommends recipe moves, dispositions and dispatch, with citationsEnters every change manuallyShadow mode, first on the design-partner cell
L2 · SupervisedProposes a recipe write or hold; it executes on approvalApproves each move in the review consoleAssist mode, where accuracy and ROI are proven
L3 · BoundedWrites inside the qualified recipe window, tool-state checks and OCAP linkageApproves holds, out-of-window moves and lot releaseGraduated autonomy for low-risk APC, defect and metrology loops
L4 · Qualified loopsRuns a qualified loop without prompting, inside its envelopeSets the envelope; reviews the shift recordPlanned; reserved for loops the fab has qualified
Guardrails

An agent that can move a recipe needs a leash

Waferira writes to production tools over SECS/GEM. Every capability is scoped to a qualified recipe window, every write is policy-checked against tool state, and every action is written to an append-only, IP-isolated audit log the fab owns.

  • Recipe bounds. Each agent writes only inside the qualified recipe window for that tool, with explicit per-parameter limits.
  • Policy and tool-state checks before every write. Autonomy level, tool state, qualification, interlocks and shift are evaluated before a recipe moves.
  • Human-in-the-loop gates. Holds, out-of-window moves and lot release wait for a named approver, with OCAP linkage on every excursion.
  • Immutable, IP-isolated audit log. Append-only and exportable. Every action records source signals, retrieved procedures with citations, predicted impact, allowed range, rollback condition, approver and lot scope.
  • Rollback. Declared rollback conditions return a recipe to its previous qualified version; loss of the edge node leaves the tool on its own controller and recipe.
  • Tenant and IP isolation. Recipes, device designs, defect libraries and process memory never cross a customer boundary. Inference and feature storage stay at the fab edge; an on-prem control plane is available for IP-sensitive fabs.

Compliance posture

Compliance and certification status
ItemScopeStatus
SOC 2 Type I and fab-security reviewControl plane QUEUED Planned, first 6 months
SOC 2 Type IIControl plane QUEUED Planned, 6 to 12 months
SSO and RBACConsole and approvals QUEUED Planned, 6 to 12 months
IP-isolation and security assurance packageFab security and IT and OT review QUEUED Planned, 6 to 12 months
SEMI-standards-cited reasoningRecipes, integration specs, OCAPs RUNNING In the design, every answer cites its source
Per-tenant IP isolationData, models, memory RUNNING In the design from day one
On-prem and fab-edge deploymentIP-sensitive fabs RUNNING Design option

Read the security overview

FAQ

Straight answers

The questions fab directors and process engineers ask in the first meeting.

Yes, over SECS/GEM, but only inside the qualified recipe window for that tool, with per-parameter limits and tool-state checks, and only at the autonomy level your fab has set. Level 1 is advisory: Waferira recommends and an engineer enters everything. Design partners start there, in shadow mode.

Get started

Tell us what you want to own

Write to hello@waferira.com with the role and what you have built.